Error fitter for PHY IP gen3

HI,

You are right. Your FPGA pin assignment setting is fine.

The problem is on your top level design connection. Below is the fix I made to your vqm design

1. Fixed broken NativePHY (tx_serial_data) connection

• I presume you want to connect to output port "DIFF100_PCIE_MOLEX_1KU12_PET" so I connect it back

1. Fixed wrong clocking connection to NativePHY for PIPE GEN 3

• fPLL tx_serial_clk should be connected to NativepHY tx_serial_clk0
  • ATX PLL tx_serial_clk should be connected to NativepHY tx_serial_clk1

You can also generate the example design directly from NativePHY IP to learn about the design connection

• Goto NativePHY -> design example tab
  • change the fPLL default frequency from 125MHz back to 100MHz
  • Then click generate example design button

Thanks.

Regards,

dlim