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Honored ContributorError: Bus name allowed only on bus line -- signal "vcprst[15..0]"
when i analysis and synthesis the boost converter programming ,then i got following error.please help me that how i rectify these error and exactly where is the error?
Error: Bus name allowed only on bus line -- signal "vcprst[15..0]"Error: Bus name allowed only on bus line -- signal "vcout[15..0]" Error: Bus name allowed only on bus line -- signal "vcprst[15..0]" Error: Bus name allowed only on bus line -- signal "vcprev[15..0]" Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 0 warnings Error: Peak virtual memory: 195 megabytes Error: Processing ended: Tue Apr 08 17:50:32 2014 Error: Elapsed time: 00:00:12 Error: Total CPU time (on all processors): 00:00:021 Reply
Altera_ForumAre you using the schematic editor?
If so, you need to highlight the entire net, then right click on it and select "Bus Line" from the popup menu. The net will now appear thicker.
