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Indra_Kumar_D's avatar
Indra_Kumar_D
Icon for New Contributor rankNew Contributor
7 months ago

Error (19117): QSPI Flash Programming Failed on AXE5-Eagle Board Using .jic File

Hi all,

I'm working with the AXE5-Eagle Agilex 5 development board and trying to program a .jic file that includes the .sof and U-Boot SPL (FSBL) using Quartus Prime Pro 24.2 on Linux.

I'm following the official AXE5-Eagle Linux flow from this GitHub link:
https://github.com/ArrowElectronics/Agilex-5/wiki/Command-Line-Linux-24.2

I generated the .jic using the following command:

quartus_pfg -c output_files/axe5_eagle_top.sof flash_image.hps.jic \
-o device=MT25QU128 \
-o flash_loader=A5ED065BB32AE4SR0 \
-o hps_path=~/u-boot-socfpga/spl/u-boot-spl.ihex \
-o mode=ASX4

Then I attempted to program it via JTAG using:

quartus_pgm -c 1 -m jtag -o "pvi;axe5_eagle_top_hps.jic@2"

But I get the following error during programming:

Error (19117): Programming failed on flash chip select 0 at address 0x00000000
Error (209012): Operation failed

Full log excerpt:
- Configuration of FPGA succeeds
- Flash erase starts, then fails at programming stage

I’ve confirmed:
- USB-Blaster is detected and working
- JTAG cable index is correct
- MSEL is currently set to JTAG (confirmed by behavior)
- .sof programming works fine via JTAG

Questions:
1. Is there a specific MSEL mode required to successfully program QSPI flash via JTAG?
2. Are there known issues with QSPI flash access on this board or Quartus 24.2?
3. Could U-Boot/SPL be holding the flash in a way that interferes with programming?
4. Any recommended `quartus.in` or cable speed settings for this setup?

Thanks in advance for any help or tips!

Configuration

3 Replies

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    7 months ago

    Hi Indra_Kumar_D,


    Thank you for the detailed description of your setup and the steps you've taken so far.

    Based on your information and typical Agilex 5 and Quartus flows, please see the following guidance for your questions:


    1. MSEL Mode for QSPI Programming via JTAG

    To program the QSPI flash via JTAG, the MSEL pins must be set to JTAG mode. This ensures the FPGA loads the necessary JTAG-to-Flash bridge (Flash Loader) for Quartus to access the flash device.

    You mentioned MSEL is set to JTAG and .sof programming works, so this appears correct.


    2. Known Issues with QSPI Flash or Quartus 24.2

    There are currently no widespread known issues with QSPI programming on Agilex 5 using Quartus 24.2 on Linux, provided all device and flash parameters are correct. Please ensure you are using the correct flash device and Flash Loader settings, as per the AXE5-Eagle documentation.


    3. U-Boot/SPL Interference

    If the HPS or U-Boot SPL is running and accessing QSPI during programming, it can interfere with the process. We recommend ensuring the HPS is held in reset or prevented from accessing the QSPI flash while programming via JTAG. Some boards have jumpers or switches to disable HPS boot or QSPI access—please consult the AXE5-Eagle board documentation for details.


    4. Quartus Programmer Settings

    • Cable Speed: Slower JTAG clock rates (e.g., 6 MHz or 3 MHz) can improve reliability when programming large flash devices.
    • quartus.ini: You can enable additional debugging by adding the following to your quartus.ini file:
    • [Quartus II Programmer]
    • JTAGChainDebug = ON
    • USB-Blaster: Make sure you have the correct permissions (udev rules) if running on Linux.


    Additional Recommendations:

    • Double-check that the generated .jic file is targeting the correct flash device and using the proper flash loader.
    • If possible, try erasing the QSPI flash before programming.
    • Ensure board power rails are stable.
    • Verify any board jumpers or switches related to flash write protection or HPS boot.


    If the issue persists, please provide the full Quartus command output (with debug enabled), your board revision, and any relevant jumper settings. We’ll be happy to assist further.


    Best regards,

    Fakhrul


  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    7 months ago

    As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.


  • Anonymous's avatar
    Anonymous
    5 months ago

    Hi.

    There is a known issue with the Linux driver for the "Arrow USB Programmer" when programming .jic files.

    Ref the section about Linux=>Known Issues on this page: Arrow USB Programmer - Public Docs - Trenz Electronic Wiki

    Known issues

    • During the enumeration process, the FTDI USB controller performs a reset. Depending on the hardware used, this might remove the power from the FPGA and therefore might erase the contents of the FPGA.
    • udev rules has default priority 50 for usb device. In case of trouble increase priority
      • check if usb devices has RW rights: ls -la /dev/bus/usb/001/*
    • non-volatile (.jic) configuration does not work with Linux OS and Agilex FPGA (The problem is still being investigated)
      • Workaround: Use volatile (.sof) configuration or Win OS

    As it states:

    The Workaround is to program the .jic from a Windows machine.