Error (10819)

Hello.

I want to generate a simple square wave with the system clock at 135 MHz.

The "rechteck_out" vector is interpreted as "Signed(Two's complement)".

I get the following error message after compiling:

Error (10819): Netlist error at rechteck.vhd(25): can't infer register for rechteck_out[16] because it changes value on both rising and falling edges of the clock.

This is my vhdl-code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

ENTITY rechteck IS

PORT(

clk : IN STD_LOGIC;

rechteck_out : OUT STD_LOGIC_VECTOR(20 DOWNTO 0)

);

END rechteck;

ARCHITECTURE behavior OF rechteck IS

BEGIN

PROCESS(clk)

BEGIN

IF (clk'event and clk = '1') THEN

rechteck_out <= "100000000000000000000";

ELSIF (clk'event and clk = '0') THEN

rechteck_out <= "011111111111111111111";

END IF;

END PROCESS;

END behavior;

Could you please help me to solve this problem...

Thanks.