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Altera_Forum
Honored Contributor
Honored ContributorError (10819)
Hello. I want to generate a simple square wave with the system clock at 135 MHz. The "rechteck_out" vector is interpreted as "Signed(Two's complement)". I get the following error messa...
Altera_ForumHonored Contributor
Honored ContributorHello tobias,
as always Gurus are right ( otherwise they would not be gurus :) )... no way to get a F\F triggering on both clock edges... such a shame... If you have a 135MHz clock input you can generate a 67,5 MHz squarewave feeding the D input with the inverted Q output of a F\F and clocking it @ 135MHz. If you really need a 135MHz squarewave ( that is the reproduction of the input clock btw ) you can either buffer it, or feeding a PLL macrofunction IN pin with it and set a 1\1 input\output ratio, or feeding a PLL macrofunction IN pin with it and set a 1\2 input\output ratio and feeding the OUT to clock a F\F arranged as before, or ... etc. etc. I can go on with examples but I assume the concept is clear :)
