Error (10198): Verilog HDL error at altera_merlin_width_adapter.sv

I created a Qsys component in VHDL where the rest of my design is in verilog. I created the Qsys system and I try to do a synthesis and get the following cryptic error :

Error (10198): Verilog HDL error at altera_merlin_width_adapter.sv(433): part-select direction is opposite from prefix index direction

Error (10784): HDL error at altera_merlin_width_adapter.sv(432): see declaration for object "int_ratio_minus_1"

Error (12152): Can't elaborate user hierarchy "embedded_system:u0|embedded_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:width_adapter_001"

And those lines (432 and 433) are the following:

wire [31:0] int_ratio_minus_1 = (cmd_burst_size/OUT_NUMSYMBOLS) - 1;

wire [clogb2(RATIO)-1:0] sized_ratio_minus_1 = int_ratio_minus_1[clogb2(RATIO)-1:0];

Any clues what is wrong?

Salman