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Honored Contributor
Honored ContributorError (10198): Verilog HDL error at altera_merlin_width_adapter.sv
I created a Qsys component in VHDL where the rest of my design is in verilog. I created the Qsys system and I try to do a synthesis and get the following cryptic error : Error (10198): Verilog ...
Altera_ForumHonored Contributor
Honored ContributorNever mind...i was using a 24-bit write and readdata bus...once I fixed it to 32, errors gone.
