New Contributor
New ContributorThanks for the reply.
No I did not set the I/O (as far as I know)
I tried the 'Pin Planner' approach but 'Show IO Banks' and 'Show VRef Groups' on the <RightClick> menu is greyed out and the Node list at the bottom does not show any voltage setting (as other devices have done).
I have just found that if I select a pin and <RightClick>'Pin Properties' I get a window where the I/O Standard is '3.3-V LVTTL(default)' but it can be changed to 'TTL'. (Only if the pin is assigned to a node)
Altenatively I can select a node and do a similar thing but still individually.
Presumably if I change this for all pins I should be able to compile.
It would help if there is a way to change the default for all pins before I assign nodes to pins.
New ContributorUnfortunately changing all the nodes to TTL did not get rid of the error. Possibly there were some (unused) pins still with the 3.3V setting (default). I did see that most pins on the top (Block) level now had TTL label (similar to pin number) attached but could not see how to add or remove that label from there.
For some reason I seem to be getting fewer resources used when compiling the same source file than before. It seems my mods have somehow lost parts of the design. I shall start again from scratch and start with the EPM7128 (which worked before) before trying the EPM7064 again. It should only need 32 cells but the epm7032 is a bit too tight.
It is puzzling to me that the 7 series devices are 5V/TTL IO but that Quartus doesn't know this and applies an incorrect default in this case. Then it throws an error rather than a warning.
I'm sure there must be a simple answer but I can't see it yet.
Regular ContributorAre there directives in your project's .qsf file (where all the settings are stored) that set the I/O type on pins or set a default I/O type to LVTTL-3.3V by accident?
For reference here is my design .qsf file for an EPM7064STC44-10 that compiles just fine on 13.0sp1.
I don't do anything that changes the I/O type on any pins.
DESIGN.qsf:
# Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. set_global_assignment -name FAMILY MAX7000S set_global_assignment -name DEVICE "EPM7064STC44-10" set_global_assignment -name TOP_LEVEL_ENTITY EPM7064S set_global_assignment -name VERILOG_FILE ../src/EPM7064S.v set_global_assignment -name SDC_FILE EPM7064S.sdc set_global_assignment -name TIMEQUEST_REPORT_SCRIPT timing_reports.tcl set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 75000 set_global_assignment -name SEED 42 set_global_assignment -name FITTER_EFFORT "Standard Fit" set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3.0 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name CRC_ERROR_CHECKING OFF set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_global_assignment -name USE_CHECKSUM_AS_USERCODE ON set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE ON set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" set_instance_assignment -name SLOW_SLEW_RATE -to IO[*] OFF # placement # top set_location_assignment PIN_34 -to IO[26] set_location_assignment PIN_35 -to IO[27] ###_location_assignment PIN_36 -to GND set_location_assignment PIN_37 -to CLK set_location_assignment PIN_38 -to OE_N set_location_assignment PIN_39 -to CLR_N set_location_assignment PIN_40 -to CLK2 ###_location_assignment PIN_41 -to VCC set_location_assignment PIN_42 -to IO[0] set_location_assignment PIN_43 -to IO[1] set_location_assignment PIN_44 -to IO[2] # left ###_location_assignment PIN_1 -to TDI set_location_assignment PIN_2 -to IO[3] set_location_assignment PIN_3 -to IO[4] ###_location_assignment PIN_4 -to GND set_location_assignment PIN_5 -to IO[5] set_location_assignment PIN_6 -to IO[6] ###_location_assignment PIN_7 -to TMS set_location_assignment PIN_8 -to IO[7] ###_location_assignment PIN_9 -to VCC set_location_assignment PIN_10 -to IO[8] set_location_assignment PIN_11 -to IO[9] # bottom set_location_assignment PIN_12 -to IO[10] set_location_assignment PIN_13 -to IO[11] set_location_assignment PIN_14 -to IO[12] set_location_assignment PIN_15 -to IO[13] ###_location_assignment PIN_16 -to GND ###_location_assignment PIN_17 -to VCC set_location_assignment PIN_18 -to IO[14] set_location_assignment PIN_19 -to IO[15] set_location_assignment PIN_20 -to IO[16] set_location_assignment PIN_21 -to IO[17] set_location_assignment PIN_22 -to IO[18] # right set_location_assignment PIN_23 -to IO[19] ###_location_assignment PIN_24 -to GND set_location_assignment PIN_25 -to IO[20] ###_location_assignment PIN_26 -to TCK set_location_assignment PIN_27 -to IO[21] set_location_assignment PIN_28 -to IO[22] ###_location_assignment PIN_29 -to VCC set_location_assignment PIN_30 -to IO[23] set_location_assignment PIN_31 -to IO[24] ###_location_assignment PIN_32 -to TDO set_location_assignment PIN_33 -to IO[25] # the end
New ContributorHi There.
Well, deleted everything (all project folder) and re-entered design from scratch. (Part block, part verilog)
Now it works! - Compiles without error, Node properties are TTL(default).
No idea where the previous default originated.
Thanks for your comments and replies.
Regular ContributorWell it is unfortunate that you deleted your existing .qsf file without posting the contents.
I suspect at some point set I/O type to LVTTL 3.3V was inadvertently added on some pins.
Would have been interesting to confirm that.
Good that you got your design working again, but that was kind of the "reformat-your-hard-disk-and-reinstall-your-os" solution.
New ContributorSorry but got a bit desparate and resorted to the sledgehammer. The only thing I can offer is that all the pins had the '3.3-V LVTTL(default)' setting. I now see 'set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL' at the end of the .qsf file.
Looking through some previous projects I found that one compiled for EPM240 had 'set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"' which seems odd. Others compiled for EPM7128 had no entry in the .qsf for IO standard.
At no time had I specified a IO previously.
