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Altera_Forum's avatar
Altera_Forum
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10 years ago

EPM2210 state of I/O pins during configuration time of the CPLD upon power up

Regarding the MAX II CPLD family, the EPM2210 CPLD:

At power on during the configuration time of the CPLD, what is the default state of all its I/O pins?

From the datasheet, i have read that during the configuration time of the CPLD, all I/O pins are tri-state with an internal weak pull up.

I will like to verify if this is correct.

And if it is, can i configure these I/O pins to tri-state with a weak pull down instead.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I think you can put a pull down resistor external to the FPGA to get what you need. Be sure to use a value that can be overridden by the current available.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You can't change the pull-ups during the download period at power on. Prior to the device being configured all I/O pins will have a weak pull-up enabled.

    Once the device has booted with your design you can disable the pull-up. However, you can't add a pull-down internally. As Galfonz says, you'll have to add an external pull-down.

    Cheers,

    Alex