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Altera_Forum
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9 years ago

EPM2210 state of I/O pins during configuration time of the CPLD upon power up

Regarding the MAX II CPLD family, the EPM2210 CPLD: At power on during the configuration time of the CPLD, what is the default state of all its I/O pins? From the datasheet, i have read that dur...
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Altera_Forum
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9 years ago

I think you can put a pull down resistor external to the FPGA to get what you need. Be sure to use a value that can be overridden by the current available.