Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHowdy!
Been a loooong time since but I've got another question on the EPC1 (and 2) \INIT_CONF reset. From what I gather the config device will pulls this low to initiate configuration as it's connected to \CONFIG on the FPGA. Now, with \INIT_CONF being open drain, I should be able to connect this to a PMIC reset output, correct? That way, the FPGA gets configured first whereas the pushbutton device on the PMIC would re-initiate the config phase. Nice thing about this is that I can use CONF_DONE to hold my CPU in reset. Question I have is what happens when I hit reset *during* the configuration phase? Does that mess everything up? Cheers, -Mux