Honored Contributor
Honored ContributorWhat do you mean by "POR" exactly? For me it is Power-On Reset and isn't a pin on the FPGA.
DEV_OE and DEV_CLRn are pins that can be optionally used to control all the FPGA tristate outputs and clear its registers. INIT_DONE as its name indicates says if the FPGA as finished reading its configuration and switched to the application. Some FPGA can regularly check their configuration while in user mode for errors (due to bit changes caused by radiation) if an error is found it can be indicated through the CRC_ERROR pin. All those pins can be used as regular i/o if you don't need their specific function.
