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Altera_Forum
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15 years ago

EP3C120F780 FPGA Device max speed

I have a Cyclone III Development Board with the EP3C120F780C7N FPGA part# . The datasheet specs the part at 437.5 MHz for the "Clock Tree Performance". The development board has 50 MHz and 125...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for the reply. OK, so I'm at least in the ballpark for the performance I should expect to get. I did not realize that there was such an art to laying out a design. The 437.5 MHz number in the data sheet is a bit misleading at face value.

I don't know what clock domain crossings are...I'm running everything off of the one clock generated by the PLL. Is this something that I may encounter?