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I have a Cyclone III Development Board with the EP3C120F780C7N FPGA part# . The datasheet specs the part at 437.5 MHz for the "Clock Tree Performance".
Is 100 MHz truly my limit with this device?
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The performance you can achieve on any FPGA design is directly related to the depth of logic and the utilization of the device.
If you have deep logic, your FMAX can be improved by pipelining the design.
If your design is using a high percentage of the resources, timing suffers, because routing usually needs to increase to connected the LE's.
I have several EP3C designs completed, and I regularly achieve design speeds of 160 MHz and above. However, I have some designs that have difficulty achieving 80 MHz, due to the above two issues.
For the first case, just looking at the failing path, and adding register pipeline stages where possible to split the deep logic can solve the issue.
For the second, going to a larger device, or using floor-planing to limit where timing critical logic can be placed is the way to go.
Other issues that will show up as timing violations is multiple clock domain crossings. Make sure you properly cross the domains with synchronizers to avoid metastability, then you may be able to false path these errors.
Regards,
Pete
Honored Contributor
