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Altera_Forum's avatar
Altera_Forum
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10 years ago

EP2S60F1020 device testing

Hello I am doing functional testing of EP2S60F1020 using JTAGAfter doing power up pins are getting auto assign as per program. BSDL file downloaded from net is not working. Please help. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Depending on the configuration scheme chosen, the FPGA will always try to configure at power up. If there's a valid configuration image then it will always boot and assign the pins 'as per program'. I assume that's what you refer to.

However, you should always be able to take control of the FPGA, via JTAG. Occasionally BSDL files have faults in them. However, with a mature series, like Stratix II, this shouldn't be the case.

Download the BSDL file again. Make sure you take it from the "stratix ii bsdl files (https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/stratix2.html)" page.

Cheers,

Alex