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Altera_Forum
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19 years ago

EP1C3T100C8N FPGA configuration problem

Hi everybody, In my design I use an EP1C3T100C8N cyclone which gets configured from an EPCS1 serial device. EPCS1 is programmed from an external microcontroller that gets the data stream f...
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Altera_Forum
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19 years ago

I made some further investigation by looking at the signals involved in serial configuration.

Now I know exactly when the cycle repeats:

The first 128 bytes of my configuration file are:

FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6ADEFF4000682F03006ADEFF4000682F03006ADEFF4000682F030000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4455544455557475577775577675567675577765566665563625522225D2E3551A1551111551111551111551

After receiving the first 44 bytes of data, FPGA switch nCS back to high level and DCLK stops to run.

It seems there may be something wrong in the first 44 bytes (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6ADEFF4000682F03006ADEFF4000682F03006ADEFF4000682F030000)

Perhaps this header (if we can call this header) is not matching the one of EP1C3T100C8N device??

In Quartus II I have specified EP1C3T100C8 without N (it seems it is not possible to specify N)

Whitebird