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Are you referring to the PCI MAX II development board?
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It is just called MAX II Development Kit on the box but it does have a PCI edge connector.
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I reviewed the
usb_referencedesign example. It's not extraordinary instructive, but not based on auto-generated design files.
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For a project not based on auto-generated files, it sure has a lot of files that look like this:
// ***********************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.1 Build 208 09/10/04 SP 2 SJ Full Version
// ***********************************************
(That one was from USB_RD_UFM.v)
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Did you understand, that it uses a schematic entry (*.bdf) top entity? lpm_bustri isn't used as "USB transceiver" but simply the standard component in schematic entry that's available to interface the FT245 data bus. In a VHDL design, you would most likely use a behavioral description for it.
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Yeah I got that. The reason I figured it was used as the USB transceiver is that when I look in the RTL Viewer, the 8-pin I/O bus called usb_d[7 ..0] hooks up to USBDataTri:inst7, which, when opened, contains only lpm_bustri:lpm_bustri_component
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As a general suggestion, if you have difficulties to understand what the reference design is doing, design a VHDL interface to the FT245 bidrectional FIFO interface from the scratch, using the detailed FTDI datasheet.
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Sure, but it's rather the other way around. I
want to design a VHDL interface to the FTDI chip but don't know how, so I figured I'd look at the code example, which makes use of autogenerated interfaces.
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