EMIF parameters for running DDR4 at DDR 800 rate

Hi Adzim,

I have attached the snips of the IP configuration as its not allowed to upload .ip files. If there is an email I can send it to, please let me know. The current RDIMM is MTA36ASF2G72PZ – 16GB with its base part MT40A1G4.

The FPAG part is 1SG10MHN3F74C2LG. This is a dual die FPGA and the same design is across both the die. Each design has two DDR4 EMIF interfaces. All the 4 interfaces use the same IP.

I started with Quartus Pro 21.2, updated to Quartus Pro 22.3 and now Quartus Pro 22.4. When I started, one controller would calibrate and other would not in each die. With some board parameter changes, both the controllers calibrate in die U1 while in die U1 one controller calibrates and one does not.

This is the primary issue.

Beyond this, I want to increase the size to 64 GB but when I increase the size to 64GB (add address bit mem_a[17]) the implementation fails for pin assignment and Quartus suggests the exact same pin for both the controllers (in each die).

I tried to come up with a 32GB implementation to access 32GB out of the 64GB module. As RAS is shared with a[16] the implementation goes through. I tied the 18th address bit (a[17] to '0'). This implementation does not pass calibration.

So the another issue is how to access 32GB out of the 64GB.

And finally get a pinout for 64GB for board re-spin.

Please let me know if I can provide any further information.

Thanks.

Bharat