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Honored Contributor
Honored ContributorEmbedding SDC constraints in Verilog HDL source code
Is it possible to embed SDC constraints ourself using verilog HDL source code? If yes, can someone tell me how to do?
3 Replies
Altera_Forumis it somehow possible to attach a timing contraint to a reg definition?
I've found this:
on: quartushelp.altera.com/10.0/mergedProjects/hdl/vlog/vlog_file_dir_attribute.htm but I believe that's only working with classic timing analyser. is there something an equivalent for timequest??reg q2; // Equivalent to set_instance_assignment -name CUT ON -from q1 -to q2 (* altera_attribute = "-name CUT ON -to q2" *) reg q1;- Altera_Forum
Thanks for your quick reply....This is exactly what I want....
- Altera_Forum
I believe you use a Verilog attribute statement ...
Jake(* ALTERA_ATTRIBUTE = “-name SDC_STATEMENT set_multicycle_path -end -setup -from -to [get_registers *|REG2)
