Embedding SDC constraints in Verilog HDL source code

I believe you use a Verilog attribute statement ...

(* ALTERA_ATTRIBUTE = “-name SDC_STATEMENT set_multicycle_path -end -setup -from  -to [get_registers *|REG2)

Thanks for your quick reply....This is exactly what I want....

is it somehow possible to attach a timing contraint to a reg definition?

reg    q2;
// Equivalent to set_instance_assignment -name CUT ON -from q1 -to q2
(* altera_attribute = "-name CUT ON -to q2" *) reg q1;