Altera_Forum
Honored Contributor
Honored ContributorEmbedding SDC constraints in Verilog HDL source code
Is it possible to embed SDC constraints ourself using verilog HDL source code? If yes, can someone tell me how to do?
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Altera_ForumHonored Contributor
Honored ContributorI believe you use a Verilog attribute statement ...
(* ALTERA_ATTRIBUTE = “-name SDC_STATEMENT set_multicycle_path -end -setup -from -to [get_registers *|REG2)
