Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Embedding SDC constraints in Verilog HDL source code

Is it possible to embed SDC constraints ourself using verilog HDL source code? If yes, can someone tell me how to do?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your quick reply....This is exactly what I want....