Embedding SDC constraints in Verilog HDL source code

is it somehow possible to attach a timing contraint to a reg definition?

I've found this:

reg    q2;
// Equivalent to set_instance_assignment -name CUT ON -from q1 -to q2
(* altera_attribute = "-name CUT ON -to q2" *) reg q1;

on:

quartushelp.altera.com/10.0/mergedProjects/hdl/vlog/vlog_file_dir_attribute.htm

but I believe that's only working with classic timing analyser. is there something an equivalent for timequest??