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Altera_Forum's avatar
Altera_Forum
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17 years ago

embedded signals in modelsim

Hello,

I am synthesizing using altera and from altera (post synthesis) I am running a do file (EDA Tool Settings Synthesis) which only configures the wave window of modelsim and adds appropriate signals. The challenge is trying to get an embedded signal bus from within the code. I can use the following

add wave -r /* within the do file and see the embedded signals. They however all seem to have /regout or /data_ipd, etc. after them. If I cut and paste into (see below), all works fine:

add wave -noupdate -format Logic -height 34 -label r {/i4/\m_ovhd|temp[15]\/regout}

My question is how to succesfully place this down as a bus? I truly have tried about everything, but to no avail. i4 is the instance of the tesbench called within the testbench file, m_ovhd is the instance of a module with the top level vhdl file and temp[15 downto 0] is the signal of interest. Any ideas??

Thanks much,

Steve

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I also had this problem in the past. My solution was to create a bus in the testbench and assign the elements of the bus directly through hierarchical path names.

    assign my_bus[0] = top.fpga.module1.signal0;

    assign my_bus[1] = top.fpga.module1.signal1;

    and so on.

    Hope that helps,

    Harald
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Harald,

    Please expound: My top level testbench file is gparser_tb, within this file I instantiate a vhdl file gparser(this is the top level of the design) with label i4. gparser.vhd in turn instantiates gcounter with label m_ovhd. Finally within m_ovhd I have a temp bus. With this said I have created a signal within the test bench file called junk type std logic. I have tried the following but to no avail:

    junk <= i4.m_ovhd.temp(0);

    junk <= gparser.gcounter.temp(0);

    junk <= gparser.i4.m_ovhd.temp(0);

    junk <= gparser.m_ovhd.temp(0);

    For the record I use a . in records but am not familiar with the above assignments, and temp bus is NOT a record.

    Error: ModelSim-Altera Error:# ** Error: C:/altera/72/qdesigns/psu_projects/area54/gparser.vht(60): Illegal label for selected name.

    Thanks,

    Steve
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Steve,

    I am sorry but I don't know how to do this in VHDL. I used Verilog for that and Verilog allows to access signals somewhere in the hierarchical module tree through their full path names by concatenating the instance names beginning from top separated by full stops. Maybe one of the VHDL gurus can help?

    Harald
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Maybe I'm missing something here but why don't you navigate to the signal of interest in Modelsim and add to wave file?

    In the workspace window under the sim tab will be your heirarchy. The signal names will appear in the Objects window. Just right click and choose add to wave. Or are you trying to do something completely different?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes I can add to wave all signals within design and try and find it but it is not that simple.

    {sim:/gparser_tb/i4/\\m_ovhd|temp\[0\]~263_combout\\ {-format Logic -height 17}}

    I have 2000 signals, when I am troubleshooting and looking for a clear on a flip flop I want to be able to systematically add this signal for troubleshooting without sifting through all the esoteric stuff ~263_combout.

    Thanks,