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Altera_Forum
Honored Contributor
Honored Contributorembedded signals in modelsim
Hello, I am synthesizing using altera and from altera (post synthesis) I am running a do file (EDA Tool Settings Synthesis) which only configures the wave window of modelsim and adds appropriate s...
Altera_ForumHonored Contributor
Honored ContributorSteve,
I am sorry but I don't know how to do this in VHDL. I used Verilog for that and Verilog allows to access signals somewhere in the hierarchical module tree through their full path names by concatenating the instance names beginning from top separated by full stops. Maybe one of the VHDL gurus can help? Harald
