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Altera_Forum
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17 years ago

embedded signals in modelsim

Hello, I am synthesizing using altera and from altera (post synthesis) I am running a do file (EDA Tool Settings Synthesis) which only configures the wave window of modelsim and adds appropriate s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I also had this problem in the past. My solution was to create a bus in the testbench and assign the elements of the bus directly through hierarchical path names.

assign my_bus[0] = top.fpga.module1.signal0;

assign my_bus[1] = top.fpga.module1.signal1;

and so on.

Hope that helps,

Harald