embedded signals in modelsim

Harald,

Please expound: My top level testbench file is gparser_tb, within this file I instantiate a vhdl file gparser(this is the top level of the design) with label i4. gparser.vhd in turn instantiates gcounter with label m_ovhd. Finally within m_ovhd I have a temp bus. With this said I have created a signal within the test bench file called junk type std logic. I have tried the following but to no avail:

junk <= i4.m_ovhd.temp(0);

junk <= gparser.gcounter.temp(0);

junk <= gparser.i4.m_ovhd.temp(0);

junk <= gparser.m_ovhd.temp(0);

For the record I use a . in records but am not familiar with the above assignments, and temp bus is NOT a record.

Error: ModelSim-Altera Error:# ** Error: C:/altera/72/qdesigns/psu_projects/area54/gparser.vht(60): Illegal label for selected name.

Thanks,

Steve