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Altera_Forum's avatar
Altera_Forum
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14 years ago

Embedded multiplier delay

Do embedded multipliers (by '*' VHDL operator) in Cyclone II device have delay only through "combinational logic" or do they require some 250MHz clock cycles (in Cyclone II Device Handbook I've read there is 250MHz clock inside)?

Does it take longer than 20ns to calculate for 18x18bit multiplier?

I've found similar topic, but without clear answer.

Second question is which multiplication algorithm is used by embedded multiplier?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You will need a clock. There is no internal clock, you have to provide one. The 250Mhz you've seen is the max clock frequency.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    What clock you are talking about? How to provide it? I'am only using '*' VHDL operator.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The embedded multipliers will achieve highest performs when used with it's associated registers. But they can be also used in an unregistered "combinational" mode, e.g when combining multiply and addition operation. The embedded multiplier block diagram in Cyclone hardware manual will clarify about the avaliable options.

    When inferring multipliers from HDL code, which is probably the most popular method to use it, you can control registering by performing signal assignments under a clock edge sensitive condition.

    When using multipliers at moderate clock speeds, e.g. 30 to 50 MHz, it's not generally necessary to enable registering for each multiplier output or even additionally for inputs. Timing analysis will tell you what's possible.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If I understand correctly, such VHDL code 

    c <= a * b;

    assigns a and b directly to the multiplier input, not through input register (Embedded Multiplier consists of multiplier module, input register and output register).

    So delay only depends on propagation time.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Depends on. For an output register, write: 

    if rising_egge(clk) then
  c <= a * b;
end if;

    Or input- and output register 

    if rising_egge(clk) then
  as <= a;
  bs <= b;
  c <= as * bs;
end if;