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Altera_Forum
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14 years ago

Embedded multiplier delay

Do embedded multipliers (by '*' VHDL operator) in Cyclone II device have delay only through "combinational logic" or do they require some 250MHz clock cycles (in Cyclone II Device Handbook I've read ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

If I understand correctly, such VHDL code 

c <= a * b;

assigns a and b directly to the multiplier input, not through input register (Embedded Multiplier consists of multiplier module, input register and output register).

So delay only depends on propagation time.