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Altera_Forum
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14 years ago

Embedded multiplier delay

Do embedded multipliers (by '*' VHDL operator) in Cyclone II device have delay only through "combinational logic" or do they require some 250MHz clock cycles (in Cyclone II Device Handbook I've read ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Depends on. For an output register, write: 

if rising_egge(clk) then
  c <= a * b;
end if;

Or input- and output register 

if rising_egge(clk) then
  as <= a;
  bs <= b;
  c <= as * bs;
end if;