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Honored Contributor
Honored ContributorEmbedded multiplier delay
Do embedded multipliers (by '*' VHDL operator) in Cyclone II device have delay only through "combinational logic" or do they require some 250MHz clock cycles (in Cyclone II Device Handbook I've read ...
Altera_ForumHonored Contributor
Honored ContributorYou will need a clock. There is no internal clock, you have to provide one. The 250Mhz you've seen is the max clock frequency.
