EMAC in FPGA

Hi, I have a problem. I need two Eths to the HPS and also I need NAND flash. There is a conflict in pin multiplexing between the EMAC0 and NAND. So I will use EMAC0 through FPGA (GMII mode) and EMAC1 HPS I/O Set 0 (RGMII mode). It is right?

I am not sure how to connect PHY device to the EMAC0. There is GMII full set with peer to peer interface (can be unconnected?), RX_CLK_IN, TX_CLK_IN and GTX_CLK_OUT. All three clocks are connected to the PHY device?

My last question, when I am prepearing HPS system in Qsys I must define clock frequency for EMAC0_GTX_CLK and for EMAC0_MD_CLK (tab HPS Clocks, Peripheral FPGA Clocks). I am able set EAMC0_GTX_CLK as 125 MHz (It is right? Will Qsys automatically set it?). EMAC0_MD_CLK can be set 2 MHz (not 2.5 MHz -> therefore I conclude there is clock divider with step checking).