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Altera_Forum's avatar
Altera_Forum
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12 years ago

EMAC in FPGA

Hello all,

So in my project I want to use the MAC (EMAC) in the FPGA fabric. Underneath i've posted a picture of the options Qsys gives you.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8042

This is all good. But then comes the part I don't get. When you select HPS I/O, the EMAC0 mode go's to "RGMII" and when you select FPGA the EMAC0 mode go's to "FULL". What does the Mode "FULL" mean ?

When I build this project and look at the "pin planner", it looks like it is using "GMII". But I want to use "RGMII".

Is it only possible to use the RGMII MAC in combination with using the HPS ? OR ?

I hope someone can help me with this.

Kind regards,

Hidde

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You are correct, when you expose the HPS EMAC into the FPGA, it's a GMII interface. If you want RGMII then you'll need some adapter logic to convert it over to being RGMII before exposing it to FPGA I/O. For the most part this conversion involves changing the data widths and clock rates and you might be able to find code examples on the web that already do this.

    When selecting any peripheral to wire into the FPGA fabric, "FULL" essentially means to expose everything. Some of the HPS peripherals are limited by the number of HPS I/O so when you route into the FPGA often you'll be exposing more features.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Nice. Thank you for the fast response and the info. I'm going to check it out. Probably going to use a different Ethernet PHY, one that supports GMII.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi, I have a problem. I need two Eths to the HPS and also I need NAND flash. There is a conflict in pin multiplexing between the EMAC0 and NAND. So I will use EMAC0 through FPGA (GMII mode) and EMAC1 HPS I/O Set 0 (RGMII mode). It is right?

    I am not sure how to connect PHY device to the EMAC0. There is GMII full set with peer to peer interface (can be unconnected?), RX_CLK_IN, TX_CLK_IN and GTX_CLK_OUT. All three clocks are connected to the PHY device?

    My last question, when I am prepearing HPS system in Qsys I must define clock frequency for EMAC0_GTX_CLK and for EMAC0_MD_CLK (tab HPS Clocks, Peripheral FPGA Clocks). I am able set EAMC0_GTX_CLK as 125 MHz (It is right? Will Qsys automatically set it?). EMAC0_MD_CLK can be set 2 MHz (not 2.5 MHz -> therefore I conclude there is clock divider with step checking).