Forum Discussion
Altera_Forum
Honored Contributor
14 years ago"easy stuff" - using a clock within a process...
Hey guys,
I am totally new in VHDL and got a DE2-151 for making my first experience with this stuff. So I wrote an easy program, but got a (maybe simple) error I am trying to understand. My not working code - with the following error: " Error (10500): VHDL syntax error at morse.vhd(16) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement"library IEEE;
use IEEE.std_logic_1164.all;
entity morse_1 is
port (s1: in std_logic;
seg7: out std_logic_vector(6 downto 0));
END morse_1;
architecture structure of morse_1 is
begin
if s1='1' then
seg7 <= "0000001" ;
elsif s1='0' then
seg7 <= "1000001" ;
end if;
end structure;
********************** and here the working stuff. The modifications are colored....
library IEEE;
use IEEE.std_logic_1164.all;
entity morse_1 is
port (clock, s1: in std_logic;
seg7: out std_logic_vector(6 downto 0));
END morse_1;
architecture structure of morse_1 is
begin
process (clock,s1)
begin
if s1='1' then
seg7 <= "0000001" ;
elsif s1='0' then
seg7 <= "1000001" ;
end if;
end process;
end structure;
*************************** My questions: - Why do I need a process to use an if-assignment? - Why does a process (or maybe an if-assignment) need a clock? Thx to all helping replys.... Mike2 Replies
- Altera_Forum
Honored Contributor
There are two types of statements in VHDL: concurrent and sequential.
Concurrent statements are placed directly in an architecture, and all concurrent statements are executed in parallel. Sequential statements are placed in a process and are executed one after the other. The if keyword can only be used as a sequential statement, so can only be used in a process. The concurrent equivalent would be a conditional assignment:
You don't always need a clock. If your function is just here to read an input value and provide an output depending on that value you can do it without a clock. You will require a clock when you need to have registers that must hold a valuelibrary IEEE; use IEEE.std_logic_1164.all; entity morse_1 is port (s1: in std_logic; seg7: out std_logic_vector(6 downto 0)); END morse_1; architecture structure of morse_1 is begin seg7 <= "0000001" when s1='1' else "1000001" when s1='0' else "XXXXXXX"; end structure; - Altera_Forum
Honored Contributor
thanks man... thats all I wanted to know.. ;-)