"easy stuff" - using a clock within a process...

There are two types of statements in VHDL: concurrent and sequential.

Concurrent statements are placed directly in an architecture, and all concurrent statements are executed in parallel. Sequential statements are placed in a process and are executed one after the other.

The if keyword can only be used as a sequential statement, so can only be used in a process. The concurrent equivalent would be a conditional assignment:

library IEEE;
use IEEE.std_logic_1164.all;
entity morse_1 is
  port (s1: in std_logic; 
  seg7: out std_logic_vector(6 downto 0));
END morse_1;
architecture structure of morse_1 is
  
  begin
  
  seg7 <= "0000001" when  s1='1' else  "1000001" when s1='0' else "XXXXXXX";
end structure;

You don't always need a clock. If your function is just here to read an input value and provide an output depending on that value you can do it without a clock. You will require a clock when you need to have registers that must hold a value