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Altera_Forum's avatar
Altera_Forum
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12 years ago

Easy memory latency demo using SRAM and SDRAM?

I'm teaching a course in computer architecture and I'm using the DE1 boards as a teaching aid. In previous semesters I focused more on gate-level design using VHDL but now I want to move to a higher level of abstraction. One thing I want to do is demonstrate the relative access times of SDRAM and SRAM (or on-chip memory) using simple matrix operations running on a DE1 basic computer, or a similarly simple Nios II processor. However, the simple C programs I've written show no performance difference between operations on matrices stored in SDRAM and matrices stored in on-chip memory. Should I be using tightly coupled memory to bypass the avalon switching fabric, or is there something else I'm missing?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The CPU could have a data and/or instruction cache that mask access to the external memories. Try do disable those caches or to sent their size to 0.

    If your matrix operations are complicated (especially floating point) it could be possible that most of the CPU time is used to perform those operations rather than access the memory, so you won't see a big difference. I think I would use another kind of algorithm, not very CPU intensive but very memory intensive, such as sorting an integer list.

    The tightly coupled memory interfaces can only be used to connect to memories with no wait state (generally this only includes a direct and unique connection to an on-chip memory block).

    At first I was about to suggest another kind of approach, using a DMA to read or write a memory block and show the avalon signals read back from SignalTap. I think you should be able to see the initial latency with the SDRAM, and then the fast operation once the burst mode is used.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Another option is to run functional simulation of the SDRAM model + memory controller and show waveforms.

    There is probably no need of using complex board and software setup just to show that SDRAM has higher latency that SRAM.

    Thanks,

    Evgeni
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I guess it depends on the kind of class and course... I think that a demonstration on real hardware is more pedagogic than just showing the result of a simulation, but it could be me ;)