Dynamic voltage switching IO

Hello,

I'm looking for a solution for dynamic voltage switching on StratixII I/Os.

I have some bidir signals that are by default in range 0-3.3v and when internal conditions are met they must be in the range 0-1.8v. These signals drive an external component which follows this protocol.

Since we can't dynamically change the VCCIO inside the FPGA, I have to do it differently.

I have several ideas to do this:

1/ Place these IOs (DATA[] bus) in a separate IO bank which is powered by a regulator (VCCIO=reg. output). Regulator (external componant) is then controlled by some logic in FPGA (switch_cdt signal).

2/ Place IOs in 2 separated banks 1.8v and 3.3v (DATA_18[]/DATA_33[] buses) and connect them together to DATA[] bus of external component.

The internal data bus (DATA_i[]) is routed to both bank and control signals

(to select in or out, drive strengh,..) depends on switch_cdt=0.

Since IOs in bank 1.8v will get a 3.3 voltage, is it electrically safe?

Has anyone experienced such problem?

Regards,

Drackh