Honored Contributor
Honored ContributorGood point, I should have done this a while ago. I've attached my latest test project that uses a cascaded PLL as a .zip file. Just needs to be recompiled.
There is a signal tap enabled to see the signals while writing and In system memory constants that can be used to change the parameters before re-configuring the PLL. There is also an Sources and Probes editor for triggering a Frequency reconfig, phase reconfig and to also provide a reset On power up: The first PLL will output 125MHz, and I divided it by 4 using a counter and outputted the 31.25MHz signal to a test point The second PLL will output 31.25MHz and is also brought to a via When trying to do a positive phase shift (up_dn bit ='1') as it's setup, there output of the PLL does not move with respect to the divided down 125MHz clock. When changing the Phase constant to do a negative phase shift (up_dn bit ='0'), the PLL output will change by 2 times the amount than it should. If the frequency reconfiguration is triggered, the second PLL output will reconfigure to 40MHz. The values may be changed to output any other desired frequency within the fractional PLL specifications.
