Dynamic Phase Shift Q13.1

I am currently using a Cyclone V device and was able to successfully dynamically change the frequency back and forth using the PLL Reconfiguration megafunction.

I am not getting correct results when writing to the phase register. When writing a negative phase shift, the output shifts twice as much as it should. When doing a positive shift, the output does not shift at all.

Here is what I am doing and results I've seen:

Using the sources and probes feature over the JTAG, I setup an interface into the state machine and other blocks (PLL, PLL Reconfiguration):

https://www.alteraforum.com/forum/attachment.php?attachmentid=8106

https://www.alteraforum.com/forum/attachment.php?attachmentid=8107

https://www.alteraforum.com/forum/attachment.php?attachmentid=8108

pll is setup as follows:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8109

https://www.alteraforum.com/forum/attachment.php?attachmentid=8111

advanced parameters copy and pasted here:

m-counter hi divide

4

m-counter low divide

4

n-counter hi divide

1

n-counter low divide

1

m-counter bypass enable

FALSE

n-counter bypass enable

FALSE

m-counter odd divide enable

FALSE

n-counter odd divide enable

FALSE

c-counter-0 hi divide

20

c-counter-0 low divide

20

c-counter-0 coarse phase shift

11

c-counter-0 vco phase tap

0

c-counter-0 input source

ph_mux_clk

c-counter-0 bypass enable

FALSE

c-counter-0 odd divide enable

FALSE

c-counter-1 hi divide

2

c-counter-1 low divide

2

c-counter-1 coarse phase shift

1

c-counter-1 vco phase tap

0

c-counter-1 input source

ph_mux_clk

c-counter-1 bypass enable

FALSE

c-counter-1 odd divide enable

FALSE

c-counter-2 hi divide

20

c-counter-2 low divide

20

c-counter-2 coarse phase shift

6

c-counter-2 vco phase tap

0

c-counter-2 input source

ph_mux_clk

c-counter-2 bypass enable

FALSE

c-counter-2 odd divide enable

FALSE

vco post divide counter enable

2

charge pump current (ua)

20

loop filter bandwidth resistor (ohms)

4000

pll output vco frequency

400.0 MHz

k-fractional division value (dsm)

1

feedback clock type

gclk

feedback clock mux 1

glb

feedback clock mux 2

fb_1

m counter source mux

ph_mux_clk

I have modified the state machine from AN661 so that I may choose to reconfigure the PLL to two different frequencies or phase shift by two different amounts (in either direction).

Using the following procedure I could successfully change the frequency dynamically:

1. Power unit on.

2. Choose “data_sel” (0 = 75MHz, 1=100MHz)

3. Choose “freq_or_phase” as ‘0’ (0=frequency, 1=phase)

4. Bring “start” low if it isn’t already

5. “Down_up” is a don’t care for changing the frequency

6. Raise “reset” and then bring back low (gets everything in a known good state. PLL will start out as follows 10MHz:

a. C0 = 10MHz, phase shift = 25000 ps

b. C1 = 100MHz, phase shift = 0 (used as the system clock for other logic/state machine)

c. C2 = 10MHz, phase shift = 45 degrees

7. To start a frequency reconfiguration, raise the start signal high which will initiate the state table to reconfigure the PLL.

This can be successfully done back and forth between the 75MHz and the 100MHz.

to be continued in next post (hit picture limit)