Honored Contributor
Honored ContributorHere is a signal tap screenshot of the state table writing to the PLL reconfiguration block:
https://www.alteraforum.com/forum/attachment.php?attachmentid=8112 now to change the phase of c0 only. 1. Power unit on 2. Choose “data_sel” as ‘1’ (0=0x50 counts, 1=0x18 counts) 3. Choose “freq_or_phase” as ‘1’ (0=frequency, 1=phase) 4. Bring “start” low if it isn’t already 5. Bring “Down_up” low if it isn’t already. (0=Negative shift, 1=Positive shift) 6. Raise “reset” and then bring back low (gets everything in a known good state. PLL will start out as follows 10MHz: a. C0 = 10MHz, phase shift = 25000 ps b. C1 = 100MHz, phase shift = 0 (used as the system clock) c. C2 = 10MHz, phase shift = 45 degrees 7. To start a dynamic phase shift, raise the start signal high which will initiate the state table to reconfigure the PLL. A Negative phase shift can be repeatedly sent to keep shifting the output, but the phase shift is double what is expected! A positive phase shift, however, does nothing. results writing a negative phase count of 0x50 to c0 - VCO running at 400MHz - Phase Shift Resolution = (1/400MHz)/8 = 312.5pS - Phase shift of 0x50 = 80 counts -> 80 x (312.5pS) = 25nS actual phase shift seen at output (on scope) = 50ns instead of 25ns (direction bit set to ‘0’)https://www.alteraforum.com/forum/attachment.php?attachmentid=8113 writing a positive phase count of 0x50 to c0 - VCO running at 400MHz - Phase Shift Resolution = (1/400MHz)/8 = 312.5pS - Phase shift of 0x50 = 80 counts -> 80 x (312.5pS) = 25nS actual phase shift seen at output (on scope) = 0 ns (does not move – direction bit set to ‘1’)
https://www.alteraforum.com/forum/attachment.php?attachmentid=8114 Has anyone seen anything similar? I am currently using a Cyclone V FPGA and running Quartus 13.1. Any suggestions are appreciated! Thank you
