Amir3
Occasional Contributor
2 years ago"Dual Configuration" IP-Core (MAX 10) - Timing issue
Hey,
I'm using a 10M16SAU169I7G with "Dual Configuration" IP-Core. There is 1 Clock in the design and its rate is ~14[MHz].
Timing analysis process:
At first, I got this warning:
- After setting "ru_clk" to the same rate as "CLK_UART", I got a 'Failing path' warning when the Lanch Clock is the "ru_clk" and the Latch clock is the "CLK_UART". when I click on "Locate node in the design file", I'm taken to the IP-Core design files.
I don't understand how to fix this problem.
Thanks.