"Dual Configuration" IP-Core (MAX 10) - Timing issue

This might be related to the KDB below:

Could you try to use the timing constraint stated in the KDB so that the RU_CLK runs at half the rate of the input clock.

https://www.intel.com/content/www/us/en/support/programmable/articles/000080607.html

FYI, the MAX 10 FPGA Configuration User Guide states that the Altera Dual Configuration IP generates RU_CLK that runs at half the rate of the input clock.

Best Regards,

Richard Tan

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