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Sho2301
New Contributor
New ContributorDual Configuration Intel FPGA IP Core Signals
Hi, i have a few questions regarding the signals of this IP Core. Am i correct to assume that the avmm_rcv_address sets the Offset for the register i want to read and write from, so that with avmm...
FvM
Super Contributor
Super ContributorHi,
the MAX10 Configuration User Guide refers to Avalon Interface Specification https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html for details of AVMM interface. It should answer your questions about the function of specific signals. You don't necessarily need the info when you use Platform Designer to connect the configuration IP because all signals are wired automatically. But you may need it when you write your own AVMM master to drive the interface.
Regards
Frank
the MAX10 Configuration User Guide refers to Avalon Interface Specification https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html for details of AVMM interface. It should answer your questions about the function of specific signals. You don't necessarily need the info when you use Platform Designer to connect the configuration IP because all signals are wired automatically. But you may need it when you write your own AVMM master to drive the interface.
Regards
Frank
