DSPBuilder Simulation - Mixed HDL Simulation Help

Hello Everyone!

I have a DSPBuilder VHDL generated design that is part of a larger Verilog HDL design. I was able to bring the DSPBuilder design into my overall Verilog design and instantiate it. Then I was able to run the Quartus synthesis, place and route without issue. However, I need to be able to simulate the entire design. This is where I am running into problems. What I did was create a project in Modelsim ported over all of the verilog and vhdl files that make up my design and attempted to compile them. The verilog portion was succesful but most of the VHDL files failed to compile due to Modelsim not being able to find certain libraries for example the alt_dspbuilder library. Anyone have any experience with this sort of thing? I am currently using ModelSim ALTERA 6.1g to try to perform the simualtion. Any insight in regards to simulating DSPbuilder designs as part of a larger design would be greatly appreciated. Also has anyone had any success in performing theses types of simualtions using Cadence NCSim instead of using ModelSim. If somone could point me to some examples that might be relevant to this topic would also be very helpful.

Thanks in advance!