Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

DSPBuilder Simulation - Mixed HDL Simulation Help

Hello Everyone! I have a DSPBuilder VHDL generated design that is part of a larger Verilog HDL design. I was able to bring the DSPBuilder design into my overall Verilog design and instantiate...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I remember working on a mixed language design with ModelSim Altera. Compiling the modules in both languages worked well but when the design was to be linked (vsim) then the error message occurred. I would like to recommend that you set up a very simple mixed language design and try to simulate this before spending too much time.