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Honored Contributor
Honored ContributorDSPBuilder Simulation - Mixed HDL Simulation Help
Hello Everyone! I have a DSPBuilder VHDL generated design that is part of a larger Verilog HDL design. I was able to bring the DSPBuilder design into my overall Verilog design and instantiate...
Altera_ForumHonored Contributor
Honored ContributorSnipped from the Altera web site:
The ModelSim-Altera Edition software is licensed as a single language—either VHDL or Verilog HDL for each active subscription.
