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Altera_Forum
Honored Contributor
14 years agoDSP Senior Project Question
Hey Guys, Im an EE major just starting on my BSEE senior project. It is to create an FPGA based acoustic echo canceller. We have to use a 1024 tap adaptive FIR filter. It is require...
Altera_Forum
Honored Contributor
14 years agoIn that case it could be he means apply 1024 taps as a standard FIR i.e. input stream enters a 1024 delay pipe continuously though 128 coefficients are to be update-able as one set. Each block of 128 input samples enters next block pipe and so on till the end. As such you can just add up the 8 stages in parallel to get overall sum of products per output sample. You will need to update the 128 sets smoothly without breaking the filter computation by some sort of buffering.