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Altera_Forum
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14 years ago

DSP Senior Project Question

Hey Guys, Im an EE major just starting on my BSEE senior project. It is to create an FPGA based acoustic echo canceller. We have to use a 1024 tap adaptive FIR filter. It is require...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I am not clear about the over all purpose of your filter, but if your main filter is meant to be 1024 taps and to be applied to the input stream continuously but in blocks of 128 stages x 8 then you will need to add up all the 8 outputs continuously and divide result by 8 for every single output sample.