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Altera_Forum's avatar
Altera_Forum
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14 years ago

DSP Senior Project Question

Hey Guys, Im an EE major just starting on my BSEE senior project. It is to create an FPGA based acoustic echo canceller. We have to use a 1024 tap adaptive FIR filter. It is require...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for responding to the question and for the pdfs. I didn't mention that the echo cancellation algorithm is Block NLMS. That is why he wants us to split the filter into blocks of 128. So, we would take one block of input data, send it to a filter, take another block, send it to another filter and so on.

Each block would have it's own unique coefficients. The thing i'm confused by is how to split up a fir filter and combine the outputs to obtain the equivalent filter.