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Altera_Forum
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9 years ago

Driving multiple PLLs from single clock-capable pin

Hi, I have designed a board with Cyclone-IV E FPGA (EP4CE40CF23C6N). According to this datasheet, this FPGA has 4 PLLs and 4 clock capable pins. I want to know whether it is recommended/safe to dr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It's certainly 'safe' to do so. However, there are limitations as to which clock pins can drive which PLLs.

Run a design through Quartus. Quartus will only compile your design if it's able to find resources in the device to satisfy your design's requirements. If you can't drive two (or more) PLLs from a particular clock pin Quartus will soon tell you.

Cheers,

Alex