Altera_Forum
Honored Contributor
16 years agoDriving Multiple FPGAs and Fanout (Cyclone III)
Hi,
I have a design that will comprise of 11 FPGA boards: 10 slaves and 1 master and each board is having one cyclone III FPGA. The communication between master and slaves is via a simple SRAM protocol (with addr, data, WR/RD and CS). All boards will be interconnected together on a backplane board, with about 1 inch apart. According to the electrical specifications, the input leakage current of each pin is only 10uA. Therefore, in the case of LVTTL with 4mA drive strength, theoretically one master could drive up to 400 slaves? Is this too good to believe? Also, overshoot voltage could be a problem if signals are not terminated. Altera recommended 33R series resistor on each line. Does anyone have similar experience on this? I also would like to know what is the real benefit of using LVCMOS apart from LVTTL. Any recommendation is much appreciated.